Digital-signal-waveform improvement on VLSI packaging including inductances

As the digital signal frequency in printed circuit boards (PCBs) increases, waveform distortion, or the signal integrity (SI) problem, is getting more and more serious. The reason the SI problem is becoming serious is that wires or traces need to be regarded as transmission lines which are sensitive to electric noise. In order to overcome this problem, we have proposed a novel methodology called a segmental transmission line (STL), and have shown its effectiveness using computer simulations and fundamental prototypes. However, in the STL design, the combinatorial explosion problem occurs. To solve this problem, a genetic algorithm (GA) was used to design the STL. In this article, we apply the STL to a bus system that includes inductances, which come from the very-large-scale integration (VLSI) packaging. We evaluated the STL in simulation experiments as well as actual experiments using prototypes, and obtained a maximum improvement ratio of 1.53 in the actual experiment.