Elimination of surface state induced edge transistors in high voltage NMOSFETs for flash memory devices

The abnormal leakage failure in high voltage NMOSFETs is investigated by measuring the subthreshold hump characteristics. Gated diode, width and substrate bias dependence of the I_D-V_GS characteristics, and two-terminal I-V measurements between the source and the drain reveal that the hump characteristic is caused by the surface states, not by the gate field crowding at STI edges. The numerical calculation shows that the high voltage NMOSFETs are very delicate to leakage failure by a small amount of surface state (10¹¹ /cm²), due to the thick gate oxide and very low doping concentration for high voltage operation (>25 V). A thermal oxidation with the thickness of 1.0 nm successfully eliminates the parasitic corner transistors without changing electrical characteristics of the targeted transistors in current state of the art flash memory devices.