| 基于FPGA的32位浮点FFT处理器的设计 |
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| 引用本文： | 赵忠武,陈禾,韩月秋.基于FPGA的32位浮点FFT处理器的设计[J].电讯技术,2003,43(6):73-77. |
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| 作者姓名： | 赵忠武 陈禾 韩月秋 |
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| 作者单位： | 北京理工大学,电子工程系,北京,100081 |
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| 摘 要： | 介绍了一种基于FPGA的1024点32位浮点FFT处理器的设计。采用改进的蝶形运算单元,减小了系统的硬件消耗,改善了系统的性能。详细讨论了32位浮点加法器/减法器、乘法器的分级流水技术,提高了系统性能。浮点算法的采用使得系统具有较高的处理精度。
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| 关 键 词： | 数字信号处理 快速傅里叶变换 浮点加法器/减法器 浮点乘法器 分级流水 可编程门阵列 设计 |
| 文章编号： | 1001-893X(2003)06-0073-05 |
| 修稿时间： | 2003年2月18日 |
FPGA-based Design of a 32 Bit Floating-point FFT Processor |
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| ZHAO Zhong-wu,CHEN He,HAN Yue-qiu.FPGA-based Design of a 32 Bit Floating-point FFT Processor[J].Telecommunication Engineering,2003,43(6):73-77. |
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| Authors: | ZHAO Zhong-wu CHEN He HAN Yue-qiu |
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| Abstract: | An FPGA-based design of a 32 bit floating-point FFT processor used to compute 1024 points FFT is presented.Because of the utilization of improved butterfly processor, hardware consumption is reduced and the performance is improved. The pipelining technique of 32 bit floating-point adder/subtracter and multiplier is introduced in detail, which can enhance the performance of the FFT processor.High precision is achieved due to the inherence of the floating-point algorithm. |
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| Keywords: | Digital signal processing FFT Floating-point adder/subtracter Floating-point multiplier Pipelining FPGA Design |
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