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一种用于数字助听器的次毫瓦级语音处理平台
引用本文:袁甲,陈黎明,于增辉,黑勇. 一种用于数字助听器的次毫瓦级语音处理平台[J]. 半导体学报, 2014, 35(7): 075008-5
作者姓名:袁甲  陈黎明  于增辉  黑勇
基金项目:国家高技术研究发展计划
摘    要:We present a novel audio-processing platform, FlexEngine, which is composed of a 24-bit applicationspecific instruction-set processor (ASIP) and five dedicated accelerators. Acceleration instructions, compact instructions and repeat instruction are added into the ASIP's instruction set to deal with some core tasks of hearing aid algorithms. The five configurable accelerators are used to execute several of the most common functions of hearing aids. Moreover, several low power strategies, such as clock gating, data isolation, memory partition, bypass mode, sleep mode, are also applied in this platform for power reduction. The proposed platform is implemented in CMOS 130 nm technology, and test results show that power consumption of FlexEngine is 0.863 mW with the clock frequency of 8 MHz at Vdd = 1.0 V.

关 键 词:音频处理  助听器  平台  种用  ASIP  指令集  低功耗  应用程序

A sub-milliwatt audio-processing platform for digital hearing aids
Yuan Ji,Chen Liming,Yu Zenghui and Hei Yong. A sub-milliwatt audio-processing platform for digital hearing aids[J]. Chinese Journal of Semiconductors, 2014, 35(7): 075008-5
Authors:Yuan Ji  Chen Liming  Yu Zenghui  Hei Yong
Affiliation:Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China;Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China;Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China;Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China
Abstract:We present a novel audio-processing platform, FlexEngine, which is composed of a 24-bit application-specific instruction-set processor (ASIP) and five dedicated accelerators. Acceleration instructions, compact instructions and repeat instruction are added into the ASIP's instruction set to deal with some core tasks of hearing aid algorithms. The five configurable accelerators are used to execute several of the most common functions of hearing aids. Moreover, several low power strategies, such as clock gating, data isolation, memory partition, bypass mode, sleep mode, are also applied in this platform for power reduction. The proposed platform is implemented in CMOS 130 nm technology, and test results show that power consumption of FlexEngine is 0.863 mW with the clock frequency of 8 MHz at Vdd = 1.0 V.
Keywords:application-specific instruction-set processor (ASIP)  accelerator  low power  hearing aids
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