| 一种新颖的对称式,双比特位,分栅闪存结构单元 |
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| 引用本文： | 方亮,孔蔚然,顾靖,张博,邹世昌.一种新颖的对称式,双比特位,分栅闪存结构单元[J].半导体学报,2014,35(7):074008-4. |
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| 作者姓名： | 方亮 孔蔚然 顾靖 张博 邹世昌 |
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| 摘 要： | A fully self-aligned symmetrical split-gate cell structure for 2-bit per cell flash memory with a very competitive bit size is presented. One common select gate is located between two floating gates and a pair of source/drain junctions are shared by the 2 bits. The fabrication method utilized here to create a self-aligned structure is to form a spacer against the prior layer without any additional mask. Although the cell consists of three channels in a series, the attributes from conventional split gate flash are still preserved with appropriate bias conditions. Program and erase operation is performed by using a source side injection （SSI） and a poly-to-poly tunneling mechanism respectively.
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| 关 键 词： | 单元结构 分裂 对称 闪存 栅结构 自对准结构 全自对准 制造方法 |
A novel symmetrical split-gate structure for 2-bit per cell flash memory |
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| Fang Liang,Kong Weiran,Gu Jing,Zhang Bo and Zou Shichang.A novel symmetrical split-gate structure for 2-bit per cell flash memory[J].Chinese Journal of Semiconductors,2014,35(7):074008-4. |
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| Authors: | Fang Liang Kong Weiran Gu Jing Zhang Bo and Zou Shichang |
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| Affiliation: | Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, Shanghai 200050, China;Huahong Grace Semiconductor Manufacturing Corporation, Shanghai 201203, China;University of Chinese Academy of Sciences, Beijing 100049, China;Huahong Grace Semiconductor Manufacturing Corporation, Shanghai 201203, China;Huahong Grace Semiconductor Manufacturing Corporation, Shanghai 201203, China;Huahong Grace Semiconductor Manufacturing Corporation, Shanghai 201203, China;Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, Shanghai 200050, China;University of Chinese Academy of Sciences, Beijing 100049, China |
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| Abstract: | A fully self-aligned symmetrical split-gate cell structure for 2-bit per cell flash memory with a very competitive bit size is presented. One common select gate is located between two floating gates and a pair of source/drain junctions are shared by the 2 bits. The fabrication method utilized here to create a self-aligned structure is to form a spacer against the prior layer without any additional mask. Although the cell consists of three channels in a series, the attributes from conventional split gate flash are still preserved with appropriate bias conditions. Program and erase operation is performed by using a source side injection (SSI) and a poly-to-poly tunneling mechanism respectively. |
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| Keywords: | split-gate flash 2-bit per cell self-aligned process |
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