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全差分结构低功耗CMOS运算放大器设计
引用本文:肖莹慧.全差分结构低功耗CMOS运算放大器设计[J].沈阳工业大学学报,2017,39(6):670-674.
作者姓名:肖莹慧
作者单位:中南财经政法大学 武汉学院, 武汉 430000
基金项目:中国博士后科学基金资助项目(2015T80797)
摘    要:为了减小低电源电压以及短沟道效应对放大器的影响,获得低电压高增益的放大器,提出了一种基于65 nm CMOS工艺技术的全差分运算跨导放大器(OTA).采用基于增益增强技术的折叠共源共栅拓扑结构,使放大器具有轨到轨输入及大输出摆幅特性,同时兼备高速、高增益及低功耗优点.电路仿真结果表明,其直流增益为82 d B,增益带宽为477 MHz,相位裕度为59°.正常工艺角下稳定时间为10 ns,稳定精度为0.05%,而功耗仅为4.8 m W.

关 键 词:CMOS集成电路  增益增强  运算跨导放大器  高速  高增益  低功耗  折叠共源共栅结构  高增益带宽  

Design of low power CMOS operational amplifier with fully differential structure
XIAO Ying-hui.Design of low power CMOS operational amplifier with fully differential structure[J].Journal of Shenyang University of Technology,2017,39(6):670-674.
Authors:XIAO Ying-hui
Affiliation:Wuhan College, Zhongnan University of Economics and Law, Wuhan 430000, China
Abstract:In order to reduce the influence of low supply voltage and short channel effect on the amplifier and obtain an amplifier with low voltage and high gain, a fully differential operational transconductance amplifier(OTA)based on a 65 nm CMOS technology was proposed. A folded-cascode structure with a gain enhancement technology was adopted, which made the amplifier have a rail to rail input and large output swing characteristics and such advantages as high speed, high gain and low power. The circuit simulation results show that the DC gain is 82 dB, the gain bandwidth is 477 MHz and the phase margin is 59°. In addition, the settling time is 10 ns and the settling accuracy is 0.05% under the normal process angle, while the power consumption is only 4.8 mW.
Keywords:CMOS integrated circuit  gain enhancement  operational transconductance amplifier  high speed  high gain  low power  folded-cascode structure  high gain bandwidth  
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