| 基于FPGA的数据包分类研究 |
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| 引用本文： | 瞿中. 基于FPGA的数据包分类研究[J]. 计算机工程与设计, 2006, 27(9): 1554-1556 |
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| 作者姓名： | 瞿中 |
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| 作者单位： | 重庆邮电学院,计算机科学与技术学院,重庆,400065;重庆大学,计算机学院,重庆,400030 |
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| 基金项目： | 重庆邮电学院校科研和教改项目 |
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| 摘 要： | 随着Internet规模的不断扩大和应用技术的不断进步,越来越多的业务需要对数据包进行实时快速的分类.可编程片上系统（SOPC）的设计是一个崭新的富有生机的嵌入式系统设计研究方向.在阐述可编程逻辑器件特点及其发展趋势的基础上,探讨了智力产权复用理念、基于嵌入式处理器内核和XilinxFPGA的SOPC软硬件设计技术,介绍了基于Internet的可重配置逻辑（IRL）技术并提出了设计实现方法.
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| 关 键 词： | 现场可编程逻辑门阵列 数据包分类 可编程逻辑器件 包 嵌入式系统 |
| 文章编号： | 1000-7024（2006）09-1554-03 |
| 收稿时间： | 2005-03-22 |
| 修稿时间： | 2005-03-22 |
Research on packet classification based on FPGA |
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| QU Zhong. Research on packet classification based on FPGA[J]. Computer Engineering and Design, 2006, 27(9): 1554-1556 |
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| Authors: | QU Zhong |
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| Affiliation: | 1. College of Computer Science and Technology, Chongqing University of Post and Telecommunication, Chongqing 400065, China; 2. College of Computer Science, Chongqing University, Chongqing 400030, China |
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| Abstract: | With the development of Internet and the advancement application technology,more and more business needs real-time and fast packet classification.The design of system on programmable chip(SOPC) is a new and vital aspect for the research of embedded system designing.Characters and development trend of programmable logical device(PLD) were elaborated.On this basis,the intellectual property(IP)reuse methodology and the technique for designing softwareand hardwareinSOPC based onembedded processor core and Xilinx FPGA werediscussed.Technology of Internet reconfigurable logic(IRL) was introduced.The design and implementation of IRL were also presented. |
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| Keywords: | field programmable gate array(FPGA) packet classification programmable logical device(PLD) packet embedded system |
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