一种适用于门级网表的混合式静态功耗优化方法

进入深亚微米集成电路设计阶段，静态功耗所占整体功耗的比例快速增大，使之成为当前设计流程中的关键优化步骤。该文提出一种适用于门级网表的混合式静态功耗优化方法。该方法结合了整数规划和启发式算法，以减小电路时序裕量的方式换取电路静态功耗的改善。整体优化流程从一个满足时序约束的设计开始，首先利用整数规划为网表中的逻辑门单元寻找一个较低静态功耗的最优替换单元；其次结合当前所用门单元和最优替换单元的物理和电学参数，按优先级方式逐层替换电路中所有的逻辑门节点；最后利用启发式方法修复可能出现的最大延时违规情况。整体优化流程将在上述步骤中不断迭代直至无法将现有时序裕量转换为功耗的改善。针对通用测试电路的实验结果表明，采用该方法优化后电路静态功耗平均减小10%以上，最高达26%；与其它方法相比，该方法不仅大幅降低了功耗，而且避免了优化后电路最大延时的过度恶化，其最大延时违反量小于5 ps。

A Mixed Method of Leakage Optimization for Gate-level Netlist

In deep-submicron Integrated Circuit (IC) design regime, the portion of leakage power consumption increases rapidly, therefore, leakage power optimization becomes a crucial part of circuit design flow. This paper proposes a mixed method of leakage optimization for gate-level netlist. The proposed method combines integer programming and heuristic algorithm to optimize leakage power at the cost of decreased timing slack. It starts at a given timing feasible design and finds alternative cell for each gate in the netlist with optimal power-delay sensitivity, then assigns alternative cell to individual gate during a levelized traverse on netlist according to specific rules. Finally, the proposed method performs a path-based timing recovery phase to fix timing violations. The entire flow iteratively converts timing slack to power-saving until no improvements could be gained. The benchmark results shows that our the proposed method achieves 10% on average, maximum 26% leakage power reduction while timing violation is confined within 5 ps.