(1) Strategic CAD Labs, Intel Corp., JF4-211, 2111 NE 25th Ave., Hillsboro, OR 97124, USA;(2) Adomo Inc., 19400 Stevens Creek Blvd., Cupertino, CA 95014, USA;(3) Computer Systems Laboratory, Stanford University, Stanford, CA 94305, USA
Abstract:
We present an approach for formally verifying that a high-level microprocessor model behaves as defined by an instruction-set architecture. The technique is based on a specialization of self consistency called incremental flushing and reduces the need and effort required to create manually-generated implementation abstractions. Additionally, incremental flushing reduces the computational complexity of the proof obligations generated when reasoning about out-of-order execution. This is accomplished by comparing the functional behavior of the implementation abstraction over two sets of inputs: one that represents normal operation and one that is simpler, but functionally equivalent. The approach is illustrated on a simple out-of-order microprocessor core.