Achieving Less Than 2% 3- σ Mismatch With Minimum Channel-Length CMOS Devices

Offset and speed are critical yet conflicting design parameters in high-speed amplifiers and comparators, especially those used to process the characteristically high-frequency low-amplitude signals of today's wireless transceiver systems. As device area is decreased to reduce parasitic capacitances and hence achieve higher bandwidth, random mismatches inherently increase. The proposed Survivor strategy circumvents this tradeoff by fabricating a number of small-geometry device pairs on-chip (each of which have high bandwidth) and having the IC self-select the best-matched set of devices during start-up and/or power-on-reset events and use them in critical portions of the circuit. In the experiments conducted on a prototype fabricated using a 0.6-mum CMOS technology, a mirror using the best-matched minimum channel-length pair chosen from a bank of 32 pairs (6 mum/0.6 mum) had a 3-sigma offset performance (1.94%) similar to that of a mirror using 48 mum/4.8 mum devices (1.91%) and hence a bandwidth that was 64 times higher (BW_6/0.6ap64BW_48/4.8)