DF-FPDLMS自适应滤波器的可测性设计与测试

基于加法器的测试生成,提出了直接实现形式的细粒度流水线延迟最小均方自适应滤波器的一种可测性设计的测试方案。在测试模式下,该设计通过滤波器组成模块的分层隔离及由寄存器转化成的扫描链提高了可测性;通过复用部分寄存器和加法器避免或最小化了额外的测试硬件开销。该方法能在真速下高效地侦测到滤波器基本组成单元内的任意固定型组合失效,且不会降低电路的原有性能。

Design-for-Testability and Test of DF-FPDLMS Adaptive Filter

Based on arithmetic additive generator, a kind of design-for-testability and test strategy for direct-form fine-grained pipelined delayed least mean square adaptive filter is presented. The design improves the circuit testability by insulating the filter building modules and converting registers into scan chains. Reuses of some adders and registers existing in circuit result in the elimination or minimization of the additional hardware overhead for test. The test strategy can detect any combinational stuck-at faults within the circuit basic building cell at-speed and without any degradation of the original circuit performance.