首页 | 本学科首页   官方微博 | 高级检索  
     


A 300-MHz 16-b 0.5-μm BiCMOS digital signal processor core LSI
Authors:Nomura  M Yamashina  M Goto  J Inoue  T Suzuki  K Motomura  M Koseki  Y Shih  BS Horiuchi  T Hamatake  N Kumagai  K Enomoto  T Yamada  H
Affiliation:Microelectron. Res. Labs., NEC Corp., Sagamihara ;
Abstract:A 300-MHz 16-b fixed-point digital signal processor (DSP) core LSI has been developed for video signal processing. In order to achieve high performance, the DSP core LSI employs a parallel processing architecture, 300-MHz redundant binary arithmetic units, and a sophisticated high-performance electrical design. The DSP core LSI, which was fabricated with 0.5-μm BICMOS and triple-level-metallization technology, has a 3.9 mm×4.6 mm area, and contains about 57K transistors. It consumes 2 W at a 300-MHz clock frequency with a 3.3-V power supply. Measured clock skew and critical path delay are less than 80 ps and 2.6 ns, respectively
Keywords:
设为首页 | 免责声明 | 关于勤云 | 加入收藏

Copyright©北京勤云科技发展有限公司  京ICP备09084417号