| 基于CPLD的CCD驱动时序的设计 |
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| 引用本文： | 吴海青,王晓斐.基于CPLD的CCD驱动时序的设计[J].电子工程师,2007,33(9):25-27. |
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| 作者姓名： | 吴海青 王晓斐 |
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| 作者单位： | 南京林业大学信息学院,江苏省南京市,210037 |
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| 摘 要： | CCD(电荷耦合器件)作为一种应用广泛的新型半导体光电器件,驱动时序电路的实现是其应用的关键问题。提出了基于CPLD(复杂可编程逻辑器件)实现CCD驱动电路的方法。选用Al-tera公司的MAX7000S系列CPLD作为硬件设计平台,运用VHDL对驱动时序电路进行了描述,并给出了部分程序,采用Altera公司的QUARTUSⅡ软件对所设计的驱动程序进行了仿真,并用数字示波器观察输出波形。测量和仿真的结果证明是可行的。
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| 关 键 词： | CCD 驱动时序电路 复杂可编程逻辑器件 VHDL |
| 修稿时间： | 2007-03-07 |
Design of Driving Time Circuit of Linear CCD Based on CPLD |
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| WU Haiqing,WANG Xiaofei.Design of Driving Time Circuit of Linear CCD Based on CPLD[J].Electronic Engineer,2007,33(9):25-27. |
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| Authors: | WU Haiqing WANG Xiaofei |
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| Affiliation: | College of Information Science and Technology, Nanjing Forestry University, Nanjing 210037, China |
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| Abstract: | CCD is a new semiconductor photoelectric device widely used in some fields.The design of the time sequence driving circuit of CCD is a crucial problem of its application.This paper introduced the method of designing the time sequence driving circuit based on complex programmable logic device.The CPLD was used as hardware design platform and VHDL was employed to describe the driving sequencer.The designed generator has been successfully fulfilled system simulation with QuartusII software and fitted into MAX7000S.It is also oberserved by Oscilloscape.The simulation and the results of measurement demonstrate that this method is feasible. |
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| Keywords: | CCD time sequence driving circuit CPLD VHDL |
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