A high-speed median circuit

A high-speed analog median circuit is presented using a two-stage architecture to minimize the errors around the transition corners. Prototypes have been designed and built using the Orbit 2-μm CMOS process. The design has been optimized for low crossover distortion and fast transient recovery in less than 200 ns. The active area is 0.2 mm ², and the circuit dissipates 7 mW from a single 5 V supply while being able to drive an external 30 pF capacitor