A systematic investigation of the integrated effects of gate underlapping,dual work functionality and hetero gate dielectric for improved performance of CP TFETs

This paper presents a comparative analysis of the combined effects of gate underlapping and dual work functionality with hetero gate dielectric engineering for a charge plasma tunnel field-effect transistor (CP TFET). Ultrathin nanoscale devices, despite their size and cost advantage, present serious issues, including doping control, random dopant fluctuation and fabrication complexity. Given these concerns, the concept of charge plasma is introduced to avoid the need for conventional doping for the formation of the source and drain regions, which makes the device resistive to process variation. Conduction for negative gate bias (ambipolarity), excess Miller capacitance (gate-to-drain capacitance) and poor RF performance in TFETs are addressed by the use of gate underlapping from the drain side. In addition, enhanced ON-state current is obtained by work function shifting (dual work functionality). This shift in work function can be accomplished by nitrogen doping of the gate electrode for experimental levels 1]. The combined effects of the underlap and dual work function are seen in the device having a single gate dielectric. However, the ON-state current remains lower in the case of \(\mathrm{SiO}_{2}\) as the gate dielectric. Therefore, a hetero gate dielectric \(\mathrm{SiO}_{2}\) on the drain side and \(\mathrm{HfO}_{2}\) on the source side are considered in order to improve the RF parameters and enhance the ON-current concept, respectively. Finally, the combined effects of gate underlap with work function shift and hetero dielectric are analyzed in CP TFETs. The results show that proper underlap length and gate work function provide a significant improvement in device performance. Therefore, optimization of the underlap length and work function is performed to determine the specific work function that provides overall enhancement of DC and analog/RF performance of the device. In addition, optimization of the dual work function gate length is demonstrated.