An algorithm analog-to-digital converter using unity-gain buffers

An algorithmic stage for bipolar 1-b analog-to-digital (A/D) conversion using a unity-gain buffer is proposed. Cyclic and pipeline A/D converter architectures using this stage iteratively or in cascade are also described. Error analysis and SPICE simulations show that a conversion accuracy higher than 8-b and a conversion rate up to 10 Mb/s are attainable with presently available 3-μm CMOS technologies. Video frequency operation is also possible with finer linewidths. The component requirement is minimum, and thus it is best suited for an analog interface in application-specific integrated circuits (ASIC). A prototype cyclid A/D converter built using discrete components confirms the principles of operation