一种优化FPGA布线拥塞的FHO-BP网络

超大集成电路的高度复杂化造成的布线拥塞可能导致电路的不可布性，早期的布线拥塞预测对于提高集成电路的最终设计质量非常关键，因此针对现场可编程门阵列(Field Programmable Gate Array, FPGA),引入火鹰优化(Fire Hawk Optimizer, FHO)算法机制优化反向传播(Back Propagation, BP)神经网络，提出一种基于复杂网络和FHO-BP网络的布线拥塞优化方法，将电路布局的复杂网络特征向量应用到布线拥塞度预测模型中，并利用提出的优化算法改善电路布线拥塞。实验结果表明，与经典的BP网络相比，所提FHO-BP预测模型具有更高的预测精度和收敛速度，决定系数达到92.62%,模型的平均训练时间为94.55 s,平均预测时间为0.57 s,并且利用布线拥塞优化算法对布局进行优化后的布线实际拥塞程度明显缓和。

A Fire Hawk Optimizer Based Back Propagation(FHO-BP) Network for FPGA Routing Congestion Optimization

The high complexity of very large scale integration(VLSI) physical design tends to cause routing congestion,which leads to unroutability in practice.The routing congestion prediction in the early stage becomes critical to improve the ultimate quality of the result(QoR).A machine learning-based framework using complex network features and Fire Hawk Optimizer(FHO) based back propagation(BP) neural network is proposed to predict the routing congestion of modern field programmable gate array(FPGA) design.The framework extracts the complex network features of FPGA design as the input of the machine learning model at the placement stage.An algorithm is proposed to improve the routing congestion of the design.The experimental results show that the framework achieves high prediction accuracy and fast convergence.Compared with that of the traditional BP neural network,the coefficient of determination achieves 92.62% on average.The network takes less than 94.55 s for model training and 0.57 s for prediction on average.The routing congestion is greatly improved when the proposed algorithm is applied.