Design and analysis of low power high-speed 1-bit full adder cells for VLSI applications

This paper presents a low power and high speed two hybrid 1-bit full adder cells employing both pass transistor and transmission gate logics. These designs aim to minimise power dissipation and reduce transistor count while at the same time reducing the propagation delay. The proposed full adder circuits utilise 16 and 14 transistors to achieve a compact circuit design. For 1.2 V supply voltage at 0.18-μm CMOS technology, the power consumption is 4.266 μW was found to be extremely low with lower propagation delay 214.65 ps and power-delay product (PDP) of 0.9156 fJ by the deliberate use of CMOS inverters and strong transmission gates. The results of the simulation illustrate the superiority of the newly designed 1-bit adder circuits against the reported conservative adder structures in terms of power, delay, power delay product (PDP) and a transistor count. The implementation of 8-bit ripple carry adder in view of proposed full adders are finally verified and was observed to be working efficiently with only 1.411 ns delay. The performance of the proposed circuits was examined using Mentor Graphics Schematic Composer at 1.2 V single ended supply voltage and the model parameters of a TSMC 0.18-μm CMOS.