| 高性能嵌入式UART IP核的设计 |
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| 引用本文： | 刘伟峰, 庄奕琪, 刘锋, 何威, 王英力.高性能嵌入式UART IP核的设计[J].电子器件,2007,30(4):1275-1278. |
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| 作者姓名： | 刘伟峰 庄奕琪 刘锋 何威 王英力 |
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| 作者单位： | 1. 西安电子科技大学微电子学院宽禁带半导体材料与器件教育部重点实验室,西安,710071
2. 北京大学计算机学院,北京,100871 |
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| 摘 要： | 利用有限状态自动机理论1]进行了可嵌入式UART的设计.支持AMBA 2.0 APB总线接口.采用了改进的异步FIFO,在提高传输速率的同时能够更加准确的判断出FIFO的空满状态.提出了一种新的小数分频的处理方法,操作简单,便于实现.设计通过了FPGA的仿真验证.嵌入到单板系统中,在UART时钟为12.5 M的情况下,实现了与ARM PSK系统中的UART以230 k以内的任意波特率的数据传输.试验结果证明了本设计的可行性.
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| 关 键 词： | UART 嵌入式 设计 AMBA 异步FIFO 小数分频 |
| 文章编号： | 1005-9490（2007）04-1275-04 |
| 修稿时间： | 2006-08-22 |
Design of a High Performance Embedded UART |
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| LIU Wei-feng,ZHUANG Yi-qi,LIU Feng,HE Wei,WANG,Ying-li.Design of a High Performance Embedded UART[J].Journal of Electron Devices,2007,30(4):1275-1278. |
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| Authors: | LIU Wei-feng ZHUANG Yi-qi LIU Feng HE Wei WANG Ying-li |
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| Abstract: | Based on the FSM theory,the design of an embedded UART is performed in this paper,which supports the interface of an AMBA(Advanced Microcontroller Bus Architecture) 2.0 APB(Advanced Peripheral Bus).An improved asynchronous FIFO is proposed,which can generate empty and full flags more correctly while improving the transmission speed.Also,a new approach with easy operation and convenient realization is presented to deal with the fractional frequency division.It had been tested on FPGA.Embedded in the system,it had realized the transmission of data with that of ARM PSK system at any bit rate within 230 K in the condition of UART clock 12.5 M.Results of the test prove the feasibility of the design. |
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| Keywords: | UART embedded design AMBA Asynchronous FIFO fractional baud rate |
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