| 基于预缓冲机制的低功耗指令Cache |
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| 引用本文： | 王冶,张盛兵,王党辉.基于预缓冲机制的低功耗指令Cache[J].计算机工程,2012,38(1):268-269,272. |
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| 作者姓名： | 王冶 张盛兵 王党辉 |
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| 作者单位： | 西北工业大学航空微电子中心,西安,710065 |
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| 基金项目： | 国家自然科学基金资助项目（60736012） |
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| 摘 要： | 为降低微处理器中片上Cache的能耗，设计一种基于预缓冲机制的指令Cache。通过预缓冲控制部件的预测，使处理器需要的指令尽可能在缓冲区命中，从而避免访问指令Cache所造成的功耗。对7个测试程序的仿真结果表明，预缓冲机制能节省23.23%的处理器功耗，程序执行性能平均提升7.53%。
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| 关 键 词： | 微处理器 低功耗 指令Cache 预缓冲 SimpleScalar仿真器 |
| 收稿时间： | 2011-05-27 |
Low-power Instruction Cache Based on Predict Buffer Mechanism |
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| WANG Ye
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ZHANG Sheng-bing
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WANG Dang-hui.Low-power Instruction Cache Based on Predict Buffer Mechanism[J].Computer Engineering,2012,38(1):268-269,272. |
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| Authors: | WANG Ye ZHANG Sheng-bing WANG Dang-hui |
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| Affiliation: | (Aviation Microelectronics Center,Northwestern Polytechnical University,Xi＇an 710065,China) |
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| Abstract: | This paper designs an instruction Cache based on Predict Buffer（PB） mechanism to reduce the energy consumption of on-chip Cache of the processor.It can make instruction needed by processor hit in buffer mostly by PB control component predict,thus power dissipation of instruction Cache can be avoided.Simulation result of seven benchmarks shows that PB mechanism can save more than 23.23% power and improve performance by 7.53%. |
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| Keywords: | microprocessor low-power instruction Cache Predict Buffer（PB） SimpleScalar simulator |
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