Design of the processing core of a mixed-signal CMOS DTCNN chip for pixel-level snakes

This paper introduces the processing core of a full-custom mixed-signal CMOS chip intended for an active-contour-based technique, the so-called pixel-level snakes (PLS). Among the different parameters to optimize on the top-down design flow our methodology is focused on area. This approach results in a single-instruction-multiple-data chip implemented by a discrete-time cellular neural network with a correspondence between pixel and processing element. This is the first prototype for PLS; an integrated circuit with a 9/spl times/9 resolution manufactured in a 0.25 -/spl mu/m CMOS STMicroelectronics technology process. Awaiting for experimental results, HSPICE simulations prove the validity of the approach introduced here.