Multiple fault detection in two-level multi-output circuits |
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Authors: | James Jacob Vishwani D. Agrawal |
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Affiliation: | (1) Department of Electrical Communication Engineering, Indian Institute of Science, 560 012 Bangalore, India;(2) AT&T Bell Laboratories, 600 Mountain Ave., 07974 Murray Hill, NJ, USA |
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Abstract: | It is often stated that in irredundant two-level logic circuits, a test set for all single stuck faults will also detect all multiple stuck faults. We show by a simple example that this result does not hold for multi-output circuits even when each output function is prime and irredundant. Using a result from the programmable logic array technology, we give an output ordering constraint that, if satisfied during test generation, will make a single stuck fault test set a valid multiple stuck fault test set for irredundant two-level multi-output circuits. |
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Keywords: | checkpoint faults crosspoint faults fault modeling multi-output combinational circuits |
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