Simultaneous power supply, threshold voltage, and transistor sizeoptimization for low-power operation of CMOS circuits |
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Authors: | Pant P De VK Chatterjee A |
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Affiliation: | Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA; |
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Abstract: | This paper demonstrates a new approach for minimizing the total of the static and the dynamic power dissipation components in a complementary metal-oxide-semiconductor (CMOS) logic network required to operate at a specified clock frequency. The algorithms presented can be used to design ultralow-power CMOS logic circuits by joint optimization of supply voltage, threshold voltage and device widths. The static, dynamic and short-circuit energy components are considered and an efficient heuristic is developed that delivers over an order of magnitude savings in power over conventional optimization methods |
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