A 0.9 V 92 dB Double-Sampled Switched-RC Delta-Sigma Audio ADC |
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Authors: | Min Gyu Kim Gil-Cho Ahn Hanumolu PK Sang-Hyeon Lee Sang-Ho Kim Seung-Bin You Jae-Whui Kim Temes GC Un-Ku Moon |
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Affiliation: | Broadcom Corp., Irvine; |
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Abstract: | A 0.9 V third-order double-sampled delta-sigma audio ADC is presented. A new method using a combination of a switched-RC technique and a floating switched-capacitor double-sampling configuration enabled low-voltage operation without clock boosting or bootstrapping. A three-level quantizer with simple dynamic element matching was used to improve linearity. The prototype IC implemented in a 0.13 CMOS process achieves 92 dB DR, 91 dB SNR and 89 dB SNDR in a 24 kHz audio signal bandwidth, while consuming 1.5 mW from a 0.9 V supply. The prototype operates from 0.65 V to 1.5 V supply with minimal performance degradation. |
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