A self-normalizing symbol synchronization lock detector for QPSK and BPSK

This paper presents a new lock detector structure for symbol timing recovery PLLs (Phase Lock Loops), which operate in QPSK. (Quaternary Phase Shift Keying) and BPSK (Binary Phase Shift Keying) receivers in AWGN (Additive White Gaussian Noise) channels. The lock detector requires only 2 samples/symbol, which coincide with those required for the Gardner timing error detector. Simulation results are used to characterize the detector's behavior quantitatively. Both rectangular and square-root raised-cosine baseband data pulses are treated. It emerges that the lock detector has two very useful qualities. First, it is self-normalizing, and, secondly, the channel E/sub S//N/sub 0/ ratio can be easily determined from its value when the receiver is locked. Finally, a simple hardware structure is found for the lock metric computation process, which allows for its efficient implementation within an FPGA (Field Programmable Gate Array) or ASIC (Application Specific Integrated Circuit).