Gain-Enhancement Techniques for CMOS Folded Cascode LNAs at Low-Voltage Operations

In this paper, gain-enhancement techniques suitable for folded cascode low-noise amplifiers (LNAs) at low-voltage operations are presented. By employing a forward bias and a capacitive divider at the body of the MOSFETs, the LNA circuit can operate at a reduced supply voltage while maintaining an enhanced gain due to suppression of the negative impact of the body transconductance. In addition, a $G_{m}$-boosting stage is introduced to further increase the LNA gain at the cost of circuit linearity. Using a standard 0.18-$mu{hbox {m}}$ CMOS process, two folded cascode LNAs are demonstrated at the 5-GHz band based on the proposed topologies. Consuming a dc power of 1.08 mW from a 0.6-V supply voltage, the LNA with the forward-body-bias technique demonstrates a gain of 10.0 dB and a noise figure of 3.37 dB. The measured $P_{{rm in}-1 {rm {dB}}}$ and ${rm IIP}_{3}$ are $-$18 and $-$ 8.6 dBm, respectively. For the LNA with a $G_{m}$-boosting feedback, a remarkable gain of 14.1 dB gain is achieved with a dc power of 1.68 mW.