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Verisym: Verifying Circuits by Symbolic Simulation |
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| Authors: | William Adams Warren A Hunt Jr Damir Jamsek |
| Affiliation: | (1) InnoLogic Systems, Incorporated, 150A Charcot Avenue, San Jose, CA, 95131-1102;(2) The Department of Computer Sciences, Taylor Hall, M/S C0500, The University of Texas, Austin, TX, 78712-1188;(3) IBM Austin Research Laboratory, 11501 Burnet Road, Austin, TX, 78758 |
| Abstract: | |
| Keywords: | circuit extraction symbolic simulation formal property checking memory verification |
| 本文献已被 SpringerLink 等数据库收录！ | |