| 基于SoPC的人工神经网络的硬件实现方法 |
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| 引用本文： | 潘峥嵘,张赵良,朱菊香. 基于SoPC的人工神经网络的硬件实现方法[J]. 电子测量技术, 2009, 32(6): 116-118,123 |
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| 作者姓名： | 潘峥嵘 张赵良 朱菊香 |
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| 作者单位： | 1. 兰州理工大学,电气工程与信息工程学院,兰州,730050
2. 江南大学,信息与控制工程学院,无锡,214100 |
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| 摘 要： | 提出了一种基于SoPC的神经网络的硬件实现方法，该方法以FPGA器件为硬件载体，NIOSⅡ软核处理器为CPU，Avalon片内总线为数据交换架构。研究了多层前馈神经网络在FPGA上的实现方法，描述了神经网络模块与Avalon片内总线的接口技术。整个系统在Altera的EP2C8Q208C8器件上实现，结果表明，该方法的应用不仅提高了人工神经网络的运算速度，还提高了整个系统的灵活性。
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| 关 键 词： | FPGA SoPC 神经网络 Avalon片内总线 |
Hardware implementation of an artificial neural network based on SoPC |
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| Pan Zhengrong,Zhang Zhaoliang,Zhu Juxiang. Hardware implementation of an artificial neural network based on SoPC[J]. Electronic Measurement Technology, 2009, 32(6): 116-118,123 |
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| Authors: | Pan Zhengrong Zhang Zhaoliang Zhu Juxiang |
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| Affiliation: | Pan Zhengrong, Zhang Zhaoliang, Zhu Juxiang (1. College of Electrical and Information Engineering, Lanzhou University of Technology, Lanzhou 730050; 2. School of conmunication and control engineering,Jiangnan University, Wuxi 214100) |
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| Abstract: | This paper reports on the implementation of an artificial neural network based on the SoPC. This method integrates a soft processor which named NOIS II and an in-chip buss named Avalon to a single FPGA device. It studies the implementation of the multilayer artificial neural network on FPGA and describes the interface of neural network and Avalon bus. This system is implemented with EP2C8Q208C8 of Altera. It is show that the method not only step up the operation but also increase the flexible of artificial neural network. |
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| Keywords: | FPGA SoPC |
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