Study of hardware transactional memory characteristics and serialization policies on Haswell |
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| Affiliation: | 1. Computer Science Institute, University of Campinas — UNICAMP — Brazil;2. Computer Science Departament, University of Alberta, Canada;1. Carnegie Mellon University, United States;2. University of Michigan, United States;3. Massachusetts Institute of Technology, United States;4. Advanced Micro Devices, United States;1. Informatics Institute, Federal University of Rio Grande do Sul, Porto Alegre, Brazil;2. Department of Informatics and Statistics, Federal University of Santa Catarina, Florianópolis, Brazil;1. Institut für Informatik, Johannes Gutenberg-Universität Mainz, Mainz 55128, Germany;2. School of Computational Science & Engineering, Georgia Institute of Technology, Atlanta, GA 30332, USA;1. Departamento de Ingeniería y Ciencia de los Computadores, Universitat Jaume I, Castellón, Spain;2. Barcelona Supercomputing Center (BSC-CNS) and Artificial Intelligence Research Institute (IIIA), Spanish National Research Council (CSIC), Barcelona, Spain;3. Institute of Computational Mathematics, TU Braunschweig, Braunschweig, Germany;4. Instituto de Computación, Universidad de la República, Montevideo, Uruguay |
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| Abstract: | This paper presents an extensive performance study of the implementation of Hardware Transactional Memory (HTM) in the Haswell generation of Intel x86 core processors. It evaluates the strengths and weaknesses of this new architecture by exploring several dimensions in the space of Transactional Memory (TM) application characteristics using the Eigenbench (Hong et al., 2010 1]) and the CLOMP-TM (Schindewolf et al., 2012 2]), benchmarks. This paper also introduces a new tool, called htm-pBuilder that tailors fallback policies and allows independent exploration of its parameters.This detailed performance study provides insights on the constraints imposed by the Intel’s Transaction Synchronization Extension (Intel’s TSX) and introduces a simple, but efficient policy for guaranteeing forward progress on top of the best-effort Intel’s HTM which was critical to achieving performance. The evaluation also shows that there are a number of potential improvements for designers of TM applications and software systems that use Intel’s TM and provides recommendations to extract maximum benefit from the current TM support available in Haswell. |
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