BiLink: A high performance NoC router architecture using bi-directional link with double data rate |
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| Affiliation: | 1. Department of Electronic and Computer Engineering, Hong Kong University of Science and Technology, Hong Kong;2. Department of Micro- and Nano- Electronics, Shanghai Jiao Tong University, Shanghai, China;1. University of Pisa, Department of Information Engineering, Largo Lucio Lazzarino 1, 56122 Pisa, Italy;2. Politecnico di Torino, Department of Automatics and Informatics, Corso Duca degli Abruzzi 24, 10129 Torino, Italy;1. School of Mathematics and Physics, Suzhou University of Science and Technology, Suzhou, PR China;2. State Key Laboratory of Rail Traffic Control and Safety, Beijing Jiaotong University, Beijing 100044, PR China;3. Department of Applied Mathematics, The Hong Kong Polytechnic University, Hung Hum, Hong Kong;4. College of Mathematics and Statistics, Shenzhen University, Shenzhen, PR China;1. State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, PR China;2. University of Chinese Academy of Sciences, Beijing, PR China;1. School of Computer Science and Engineering, Nanjing University of Science and Technology, China;2. Department of Electronic Engineering, The Chinese University of Hong Kong, Shatin, Hong Kong;3. School of Electronic Engineering, University of Electronic Science and Technology of China, Chengdu, China;4. TCL Corporate Research (Hong Kong) Co., Limited, Hong Kong |
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| Abstract: | This paper presents a novel high performance Network-on-Chip (NoC) router architecture design using a bi-directional link with double data rate (BiLink). Ideally, it can provide as high as 2 times speed-up compared with the conventional NoC router. BiLink utilizes an extra link stage between routers and transmits two flits in one link per cycle using phase pipelining if both routers require to use the current link. To further increase the effective bandwidth, the direction of each link can be configured in every clock cycle to cater for different traffic loads from each side. Therefore, the data rate can be as high as 4 times compared with conventional NoC routers under uneven traffic. Centralized mode control scheme is implemented using a finite state machine (FSM) approach. Cycle-accurate simulations are carried out on both synthetic traffic patterns as well as real application benchmarks. Simulation results show that BiLink can provide as high as 90% and 250% speedup compared with conventional NoC routers for even and uneven traffic, respectively. 2X and 3X gains in throughput are obtained under even and uneven traffic, respectively, when compared with the conventional NoC router for the virtual channel flow control. The BiLink router architecture is synthesized using TSMC 65 nm process technology and it is shown that an area overhead of 28% over state-of-the-art bi-directional NoC is introduced while the critical path is about 9% higher than that of the conventional routers. Despite the overhead in critical path and power consumption, a 47.45% improvement of Energy-Delay-Product (EDP) is achieved by BiLink under high injection rate traffic. |
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| Keywords: | Network-on-Chip (NoC) Bi-directional link Double data rate |
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