Debugging hardware designs using dynamic dependency graphs |
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| Affiliation: | 1. University of Bremen, Bibliothekstr. 1 (MZH), 28359 Bremen, Germany;2. German Aerospace Center, Robert-Hooke-Str. 7, 28359 Bremen, Germany;1. Department of Electrical and Computer Engineering, Faculty of Engineering, NUS, Singapore;3. TU Dresden, Center for Advancing Electronics Dresden (cfaed), Germany;4. School of Electronics and Computer Science, University of Southampton, UK;1. Northeast Forestry University, Heilongjiang Institute of Technology, Harbin, China;2. Michigan Technological University, Michigan, China;3. Harbin Engineering University, Harbin, China;1. Shandong University, Weihai, China;2. Department of Multimedia, Sungkyul University, Korea;3. Information & Communication Company of Hunan EPC, Changsha, China;4. School of Computer Science, Harbin Institute of Technology, Harbin, China;1. Department of Electrical, Computer and Biomedical Engineering, via Ferrata 5, I-27100 Pavia, Italy;2. Dipartimento di Scienze del Sistema Nervoso e del Comportamento, via Forlanini 6, I-2700 Pavia, University of Pavia, Italy |
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| Abstract: | Debugging is a time consuming task in hardware design. In this paper a new debugging approach based on the analysis of dynamic dependency graphs is presented. Powerful techniques for software debugging, including reverse debugging, dynamic forward and backward slicing, and spectrum-based fault localization are combined and adapted for hardware designs. A case study on designs with multiple faults approved the power of the proposed debugging methodology reducing the debugging time to 50% in comparison to conventional techniques. |
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