An efficient VLSI architecture for lifting based 1D/2D discrete wavelet transform |
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| Affiliation: | 1. CEA, LIST, Software Reliability and Security Laboratory, P.C. 174, Gif-sur-Yvette, 91191, France;2. LAMIH, University of Valenciennes and Hainaut-Cambrésis, 59300 Valenciennes, France;3. Sherpa Engineering, 12 avenue de Verdun, F-92250 La Garenne-Colombes, France;4. ALL4TEC - Immeuble Odyssée - Bât E - 2-12 rue du Chemin des Femmes, 91300 MASSY, France;5. Continental Automotive France SAS, Division I B&S, PG3 CFT, 1 Avenue Paul Ourliac, 31036 Toulouse, France;1. School of Electrical and Electronic Engineering, Engineering Campus, Universiti Sains Malaysia, 14300, Penang, Malaysia;2. Collaborative Microelectronic Design Excellence Centre (CEDEC), Engineering Campus, Universiti Sains Malaysia, 14300, Penang, Malaysia;1. School of computer engineering and science, Shanghai University, Shanghai 200444, China;2. College of Information Science and Engineering, Guilin University of Technology, Guilin 541004, China |
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| Abstract: | In this paper, high performance VLSI architectures for lifting based 1D and 2D-Discrete wavelet transforms (DWTs) are proposed. The proposed logic used for area efficient lifting based DWT is to perform the whole operation with one processing element. Similarly, the proposed logic used for delay efficient lifting based DWT is to perform the whole operation with multiple processing elements in parallel. In both the cases, the processing element consists of one floating point adder and one proposed fused multiply add design. The proposed and existing lifting based 1D and 2D lifting based DWTs are implemented with 45 nm technology. The results show that the proposed designs achieve significant improvement compared with existing architectures. For example, 9-point 2-parallel proposed (9, 7) single level 1D-DWT achieves 33.5% of reduction in total cycle delay compared with direct form. Similarly, 9-point single PE proposed (9, 7) single level 1D-DWT achieves 59.8% and 75.5% of reduction in total area and net power over direct form respectively. |
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