HNCP: A many-core microprocessor ASIC approach dedicated to embedded image processing applications |
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| Affiliation: | 1. Northeast Forestry University, Heilongjiang Institute of Technology, Harbin, China;2. Michigan Technological University, Michigan, China;3. Harbin Engineering University, Harbin, China;1. Shandong University, Weihai, China;2. Department of Multimedia, Sungkyul University, Korea;3. Information & Communication Company of Hunan EPC, Changsha, China;4. School of Computer Science, Harbin Institute of Technology, Harbin, China;1. Department of Electrical, Computer and Biomedical Engineering, via Ferrata 5, I-27100 Pavia, Italy;2. Dipartimento di Scienze del Sistema Nervoso e del Comportamento, via Forlanini 6, I-2700 Pavia, University of Pavia, Italy;1. Computer & System Section, Electrical Engineering Department, Aswan University, 81542-Aswan, Egypt;2. Electrical Engineering Department, Faculty of Energy Engineering, Aswan University, Egypt |
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| Abstract: | Highly regular many-core architectures tend to be more and more popular as they are suitable for inherently highly parallelizable applications such as most of the image and video processing domain. In this article, we present a novel architecture for many-core microprocessor ASIC dedicated to embedded video and image processing applications. We propose a flexible many-core approach with two architectures one implemented in CMOS 65 nm technology containing 16 open-source tiles and the other implemented in CMOS FD-SOI 28 nm technology containing 64 open-source tiles. Each tile of these architectures can choose its communication links depending on the most relevant overall parallelism scheme for a targeted application. Both chips are fully functional in simulation. The layouts are presented with frequency, area and power consumption results. Various case studies are presented to illustrate the proposed flexible many-core architectures and enable to focus on architecture exploration, instantiated scheme of parallelization and timing performance. |
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