High-performance processor design based on 3D on-chip cache |
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| Affiliation: | 1. DII, University of Pisa, via G. Caruso 16, 56122 Pisa, Italy;2. ams Italy S.r.l., Via Giuntini 13, 56023 Navacchio (Pisa), Italy;1. South China University of Technology, China;2. Guangdong University of Technology, China;3. Southampton University, UK;4. Guangzhou Institute of Advanced Technology, CAS, China;5. Shenzhen Institute of Advanced Technology, CAS, China;1. Dept. of Computer Science, University of California, Los Angeles, United States;2. School of Medicine, Yale University, United States;3. Dept. of Preventative Medicine, Northwestern University, United States;1. Universitat Politecnica de Catalunya, Barcelona, Spain;2. Barcelona Supercomputing Center, Barcelona, Spain;3. University of Padova, Padova, Italy;4. Cobham Gaisler, Gotemburg, Sweden;5. Rapita Systems Ltd, York, England;6. Spanish National Research Council (IIIA-CSIC), Barcelona, Spain;1. South China University of Technology, China;2. Shenzhen Institute of Advanced Technology, CAS, China;3. Harbin Institute of Technology, China;4. Southampton University, UK and Guangzhou Institute of Advanced Technology, CAS, China;5. University of Nevada, Las Vegas, USA;6. KTH Royal Institute of Technology, Sweden |
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| Abstract: | Interconnection becomes one of main concerns in current and future microprocessor designs from both performance and consumption. Three-dimensional integration technology, with its capability to shorten the wire length, is a promising method to mitigate the interconnection related issues. In this paper we implement a novel high-performance processor architecture based 3D on-chip cache to show the potential performance and power benefits achievable through 3D integration technology. We separate other logic module and cache module and stack 3D cache with the processor which reduces the global interconnection, power consumption and improves access speed. The performance of 3D processor and 3D cache at different node is simulated using 3D Cacti tools and theoretical algorithms. The results show that comparing with 2D, power consumption of the storage system is reduced by about 50%, access time and cycle time of the processor increase 18.57% and 21.41%, respectively. The reduced percentage of the critical path delay is up to 81.17%. |
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