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基于信息截断的低复杂度多进制LDPC码译码器
引用本文:王瑞雪,陈为刚.基于信息截断的低复杂度多进制LDPC码译码器[J].信号处理,2022,38(3):641-650.
作者姓名:王瑞雪  陈为刚
作者单位:天津大学微电子学院,天津 300072
基金项目:国家自然科学基金61671324
摘    要:针对多进制低密度奇偶校验(LDPC)码译码算法实现复杂度较高的问题,基于简化增强串行广义比特翻转译码算法(SES-GBFDA),提出将每个符号的对数似然值截断为有限值进而有效减少存储需求和计算复杂度的译码算法,即截断SES-GBFDA.对于定义在伽罗华域GF(32)上的多进制LDPC码译码器,将基本更新单元的数量由32...

关 键 词:多进制低密度奇偶校验码  译码器  现场可编程门阵列
收稿时间:2021-04-27

Low-complexity Decoder for Non-binary LDPC Codes Based on Truncated Information
Affiliation:School of Microelectronics,Tianjin University,Tianjin 300072,China
Abstract:For the high implementation complexity of non-binary low-density parity-check (LDPC) codes decoding algorithm, based on the simplified enhanced serial generalized bit flipping decoding algorithm (SES-GBFDA), a method truncating the log-likelihood value for each symbol to a finite value is proposed, which can effectively reduce the memory requirement and the computational complexity, that is, truncated SES-GBFDA. For the non-binary LDPC decoder defined on the Galois Field GF(32), the number of basic update units was reduced from 32 to 10 to complete the processing of variable node messages, thereby significantly reducing the computational complexity. A non-binary LDPC decoder defined over GF(32) with a code length of 837 symbols and a code rate of 0.85 was implemented on the field programmable gate array (FPGA). The results show that, the throughput of the decoder can reach 90 Mbps, compared with the decoder without log-likelihood value truncation, the implemented decoder reduces the consumption of look-up table and register resources by 64.5% and 76.3%, respectively, with 0.25 dB loss in decoding performance. 
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