New EEPROM concept for single bit operation |
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Authors: | J.R. Raguet R. Laffont R. Bouchakour V. Bidal A. Regnier J.M. Mirabel |
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Affiliation: | 1. Université Aix-Marseille I, IM2NP, UMR CNRS 6242, IMT technopôle de Château Gombert, 13451 Marseille cedex 20, France;2. STMicroelectronics, ZI de Rousset BP 2, 13106 Rousset, France |
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Abstract: | A new 0.56 μm2 dual-gate EEPROM transistor is presented in this paper. To optimize the cell layout, a new model based on previous work has been developed. This concept allows single bit memory operations with high density; new cell programming conditions has been defined to optimize electrical behavior. Concept has been validated in an EEPROM standard technology from STMicroelectronics and allows a cell area reduction of above 50%. With appropriate potentials, the cell produces a programming window of 4 V. Moreover, this dual-gate transistor in static mode becomes an adjustable threshold voltage transistor which can be used in logic circuit or RFID applications. |
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