Impact of strain and source/drain engineering on the low frequency noise behaviour in n-channel tri-gate FinFETs

The impact of strain-engineering on the low frequency of n-channel tri-gate FinFETs fabricated on silicon on insulator (SOI) substrates noise is reported. The work is first focused on the study of nFinFETs with a standard structure and with strain-engineered channel structures, using either global or local straining techniques, or a combination of both. A carrier number fluctuation dominant flicker noise has been observed for all devices. Whereas no clear correlation between the applied strain techniques and the 1/f noise level has been found, an unusual noise spectral density was observed for the devices with selective epitaxial grown (SEG) source and drain regions. This unusual noise behaviour has been investigated for different fin widths (0.15 μm up to 3 μm) and different temperature conditions (150 K up to 300 K). An empirical model is proposed in order to explain this unusual noise behaviour. Moreover, two Lorentzians attributed to defects in the depletion region of the silicon fin were observed, and energy level and cross-section of these defects were estimated.