| 基于FPGA的No.7信令FISU过滤 |
| |
| 引用本文： | 罗明阳,廖红云,苏凌旭. 基于FPGA的No.7信令FISU过滤[J]. 计算机工程, 2010, 36(6): 236-238 |
| |
| 作者姓名： | 罗明阳 廖红云 苏凌旭 |
| |
| 作者单位： | 重庆金美通信有限责任公司,重庆,400030 |
| |
| 摘 要： | 针对CPU处理填充信号单元(FISU)存在的缺陷，分析No.7信令系统的初始定位和FISU处理过程，提出一种基于FPGA实现FISU过滤的设计方案，给出实现的原理框图、FPGA与CPU之间的通信机制和信号处理流程，使用ISE和ModelSim软件进行仿真。仿真结果表明该方案是正确、可行和有效的。
|
| 关 键 词： | No.7信令系统 初始定位过程 填充信号单元过滤 现场可编程门阵列 |
| 修稿时间： | |
No.7 Signaling FISU Filter Based on FPGA |
| |
| LUO Ming-yang,LIAO Hong-yun,SU Ling-xu. No.7 Signaling FISU Filter Based on FPGA[J]. Computer Engineering, 2010, 36(6): 236-238 |
| |
| Authors: | LUO Ming-yang LIAO Hong-yun SU Ling-xu |
| |
| Affiliation: | (Chongqing Jinmei Communication Co., Ltd., Chongqing 400030) |
| |
| Abstract: | In allusion to the disadvantage of processing Fill-in Signal Unit(FISU) using CPU, on the basis of analyzing the process of initial aligning and FISU processing in No.7 signaling system, a new design scheme adopting Field-Programmable Gate Array(FPGA) to achieve FISU filter is put forward. The principle figures, communication mechanism between FPGA and CPU, and signal processing flow charts are carried out. ISE and ModelSim software are used to achieve simulation. Simulation result proves that the scheme is correct, feasible and effective. |
| |
| Keywords: | No.7 signaling system process of initial aligning Fill-in Signal Unit(FISU) filter Field-Programmable Gate Array(FPGA) |
| 本文献已被 CNKI 维普 万方数据 等数据库收录！ |
| 点击此处可从《计算机工程》浏览原始摘要信息 |
|
点击此处可从《计算机工程》下载免费的PDF全文 |
