基于加法生成器的低功耗测试

本文提出了一种基于算术加法生成器的测试或内建自测试的低功耗测试方法。该方法对原测试矢量进行伪格雷码编码,优化被测电路的开关活动率,从而实现低功耗测试。8位行波进位加法器和16位超前进位加法器的实验分析表明,编码后的测试矢量显著地降低了被测电路的开关活动率;基于FPGA的实验结果表明,对于8位行波进位加法器,该方法将电路的平均动态功耗降低了15．282%,对于16位超前进位加法器,则降低了12．21%。该测试方法能侦测到被测电路基本组成单元的任意组合失效;由于原电路中加法器的复用,该测试方法可将测试硬件开销降至最小,但不会降低测试性能。

Low-power test based on additive generator

A low power test approach for test or built-in self-test based on arithmetic additive generator is proposed in this paper.It encodes original test patterns in pseudo Gray code presentation to optimize the switching activity of circuit-under- test(CUT),and then result in the decrease of test power consumption.Experiments on 8-bit ripple carry adder and 16-bit carry look-ahead adder was performed and the analysis shows that the test scheme decreases the overall switching activities of CUT significantly;and the results of experimentation based on FPGA show that the test approach reduces dynamic power consmnption by an average of 15.282% and 12.21% for the two adders respectively.The test approach can detect any combinational faults within basic cell of CUT.Because of the reuse of adders in CUT,it can be implemented with minimum additional hardware overhead and without any test performance degradation.