Compact class AB CMOS current mirror

Current mirrors are, together with differential pairs, the most common analogue building blocks in modern analogue and mixed-signal integrated circuits. Desirable features of current mirrors include: low standby power dissipation, wide input and output current swings, low supply voltage requirements, accurate current copy, and high linearity. Conventional class A topologies are unable to achieve simultaneously low quiescent power consumption and wide current swings, since they have maximum input and output currents limited by the DC bias currents. To overcome this shortcoming, class AB current mirrors have been proposed, which feature maximum currents not limited by the quiescent currents and reduced sensitivity to process tolerances [1]. Unfortunately, the additional circuitry required to achieve class AB operation often increases supply voltage requirements. For instance, the most common approach to achieve a class AB CMOS current mirror requires stacking of two MOS gate?source voltages [2]. This additional circuitry also often increases standby power consumption and adds extra intrinsic capacitances at the internal nodes. Another common issue is that quiescent currents are often dependent on supply voltage, process variations or temperature [2]. Other approaches are based on SC dynamic biasing [3], requiring the generation of two non-overlapping clock signals and suffering from charge injection errors.