A 250-622 MHz deskew and jitter-suppressed clock buffer usingtwo-loop architecture |
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Authors: | Tanoi S Tanabe T Takahashi K Miyamoto S Uesugi M |
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Affiliation: | OKI Electr. Ind. Co. Ltd., Tokyo; |
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Abstract: | A 250-622 MHz clock buffer has been developed, using a two-loop architecture: a delay-locked loop (DLL) for deskew, and a frequency-locked loop (FLL) for reference frequency supply to the DLL. The DLL incorporates a current-mode phase detector which utilizes a flip-flop metastability to detect a phase difference in the order of 20 ps. A measured jitter is suppressed to less than 40 ps RMS over the operating frequency range. A DLL acquisition time of 150 ns typical is simulated at 400 MHz. A 0.4-μm CMOS technology is used to fabricate the chip |
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