| 并行分时流水线A/D转换器系统级研究 |
| |
| 引用本文： | 王友华,张俊安,余金山,王永禄. 并行分时流水线A/D转换器系统级研究[J]. 微电子学, 2010, 40(2) |
| |
| 作者姓名： | 王友华 张俊安 余金山 王永禄 |
| |
| 作者单位： | 模拟集成电路国家级重点实验室,重庆,400060;中国电子科技集团公司,第二十四研究所,重庆,400060 |
| |
| 基金项目： | 模拟集成电路国家级重点实验室基金资助项目(9140C0901080802);;国家自然科学基金资助项目(60906009);;中国博士后科学基金资助项目(20090451423) |
| |
| 摘 要： | 基于并行分时A/D转换器的理论研究,对该类型A/D转换器进行了系统行为级设计和仿真。分析了系统中并行误差及流水线A/D转换器等误差源对整个系统性能的影响。通过计算机仿真,给出了系统模块的设计参数。通过理论分析与系统仿真,为并行分时流水线A/D转换器的设计提供了理论依据和数据参考,为该类型A/D转换器提供了设计优化方向。
|
| 关 键 词： | 并行分时流水线 A/D转换器 系统建模 |
Study on Architecture of Parallel Pipelined A/D Converter |
| |
| WANG Youhua,ZHANG Jun'an,YU Jinshan,WANG Yonglu. Study on Architecture of Parallel Pipelined A/D Converter[J]. Microelectronics, 2010, 40(2) |
| |
| Authors: | WANG Youhua ZHANG Jun'an YU Jinshan WANG Yonglu |
| |
| Affiliation: | National Laboratory of Analog IC's/a>;Chongqing 400060/a>;P.R.China/a>;Sichuan Institute of Solid State Circuits/a>;China Electronics Technology Group Corp./a>;P.R.China |
| |
| Abstract: | The architecture of parallel pipelined A/D converter was studied.Non-ideal sources of the parallel pipelined A/D converter were analyzed and modeled.Degradation of system performance caused by these non-ideal sources was simulated.Based on theoretical analysis and simulation,key specifications of the main functional blocks of parallel pipelined A/D converter were provided.This work could be used as a good guidance for designing parallel pipelined A/D converter. |
| |
| Keywords: | Parallel pipeline A/D converter System modeling |
| 本文献已被 CNKI 万方数据 等数据库收录！ |
