CMOS集成时钟恢复电路设计

该文设计了一个集成时钟恢复电路，恢复时钟的频率为125MHz。通过采用电流相减技术等补偿措施，很大程度上降低了振荡器的压控增益，从而在不影响电路性能的前提下大大地降低了芯片面积。本设计采用0.25m标准CMOS工艺实现，有效芯片面积小于0.2mm2，功耗仅10mW。在各种工艺角、温度以及供电电源条件下的仿真结果均表明，该电路相位偏差小于200ps，时钟抖动的峰峰值小于150ps。该文对一个采用本时钟恢复电路的100MHz PHY系统进行流片、测试，验证了时钟恢复电路能够正常工作。

The Design of Monolithic CMOS Clock Recovery Circuit

A monolithic clock recovery circuit is proposed in this paper. The frequency of the recovered clock is 125MHz. By using of some compensation methods, such as current subtraction technology, the gain of the VCO is greatly diminished, as a result the chip area is reduced also without sacrificing the noise performance of the recovered clock. This design is implemented by a 0.25μm standard CMOS technology. The active chip area is less than 0.2mm2, and the power consumption is only 10mW. The simulation results in different temperature and process condition indicate that the phase error of the recovered clock is less than 200ps and the peak-to-peak jitter is less than 150ps. A 100MHz PHY with the proposed clock recovery circuit inside is taped out and tested. The test result shows that the clock recovery circuit works properly.