A Very Low Power Consumption, Low Noise Analog Readout Chip for Capacitive Detectors with a Power Supply of 3.3 V |
| |
Authors: | Y. Hu J. D. Berst M. Schaeffer |
| |
Affiliation: | (1) LEPSI, IN2P3/ULP, 23, rue du Loess, 67037 Strasbourg, France |
| |
Abstract: | An analog frontend block of a VLSI readout chip, dedicated to high spatial resolution X or beta ray imaging, using capacitive silicon detectors, is described. In the present prototype, an ENC noise of 343 electrons at 0 pF with a noise slope of 28 electrons/pF has been obtained for a peaking time of 10 s, a 37 mV/fC conversion gain, a 3.5 V power supply and a 150 W/channel power consumption. |
| |
Keywords: | low voltage/low power analog IC design low noise amplifiers |
本文献已被 SpringerLink 等数据库收录! |
|