Performance evaluation of the time delay digital tanlock loop architectures |
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Authors: | Omar Al-Kharji Al-Ali Mahmoud Al-Qutayri Saleh Al-Araji Prasad Ponnapalli |
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Affiliation: | 1. Department of Telecom Infrastructures and Standards, The Telecommunications Regulatory Authority, Abu Dhabi, UAE;2. Department of Communication Engineering, College of Engineering, Khalifa University, Abu Dhabi, UAE;3. School of Engineering, Manchester Metropolitan University, Manchester, UK |
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Abstract: | This article presents the architectures, theoretical analyses and testing results of modified time delay digital tanlock loop (TDTLs) system. The modifications to the original TDTL architecture were introduced to overcome some of the limitations of the original TDTL and to enhance the overall performance of the particular systems. The limitations addressed in this article include the non-linearity of the phase detector, the restricted width of the locking range and the overall system acquisition speed. Each of the modified architectures was tested by subjecting the system to sudden positive and negative frequency steps and comparing its response with that of the original TDTL. In addition, the performance of all the architectures was evaluated under noise-free as well as noisy environments. The extensive simulation results using MATLAB/SIMULINK demonstrate that the new architectures overcome the limitations they addressed and the overall results confirmed significant improvements in performance compared to the conventional TDTL system. |
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Keywords: | acquisition speed DPLL jitter lock range noise TDTL |
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