一种512 Kbit同步高速SRAM的设计

设计了一种深亚微米 ,单片集成的 5 1 2 K( 1 6K× 32位 )高速静态存储器 ( SRAM)。该存储器可以作为IP核集成在片上系统中。存储器采用六管 CMOS存储单元、锁存器型敏感放大器和高速译码电路 ,以期达到最快的存取时间。该存储器用 0 .2 5μm五层金属单层多晶 N阱 CMOS工艺实现 ,芯片大小为 4.8mm× 3.8mm。测试结果表明 ,在 1 0 MHz的工作频率下 ,存储器的存取时间为 8ns,工作电流 7m A。

Design of 512-Kbit Synchronous High-speed SRAM

The design of a deep-sub-micron monolithic integrated 512 K bit high-speed SRAM is presented in this paper.This SRAM can be integrated into SOC as IP core.A fast access time is achieved by using six-transistor CMOS memory cell,latched sense amplifier,and high-speed decoder circuit.The SRAM,having a chip size of 4.8 mm×3.8 mm,is fabricated by using 0.25 μm N-well single-poly and five-metal CMOS technology.From the measurement result,the access time of SRAM is 8 ns and the dissipation current is 7 mA when the working frequency is 10 MHz.