New clustering approach to chip floorplan using functional data |
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Authors: | Harada I. Adachi T. |
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Affiliation: | NTT, Integrated Circuit Applications Section, Electrical Communications Laboratories, Atsugi, Japan; |
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Abstract: | An approach to chip floorplanning utilising hierarchical and functional information derived using LSI logic design is described. The proposed approach adopts a methodological design process similar to that of expert designers. A new clustering method that can be divided into three phases, namely clustering, cluster classification and placement, is employed in this process. The prototype system is implemented based on AI techniques. |
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