基于可重构乘法器的FIR数字滤波器设计

讨论了一种新的乘法器结构(ReMB),并把它应用于数字FIR滤波器的设计中。在设计中,基于ReMB结构,通过改进RAG-n算法,简化FIR滤波器乘法模块的结构,减少硬件实现面积,提高速度。设计的32阶半带FIR滤波器用Verilog硬件描述语言进行描述,并综合到Xilinx公司Virtex-II系列FPGA中。从综合结果来看,提出的FIR结构可以达到面积和速度的优化。

The Design of FIR Filter Based on ReMB Block

Provides a novel design of FIR filter.It employs a RAG-n arithmetic based on Reconfigurable Multiplier Blocks.The technique is implemented in a design of a half-band 32-tap FIR filter on Xilinx Virtex-II FPGA.It is shown that,The ReMB structure and employed RAG-n arithmetic can significant reduce the area and the delay.