一种可重构体系结构用于高速实现DES、3DES和AES

可重构密码芯片提高了密码芯片的安全性和灵活性,具有良好的应用前景.然而目前的可重构密码芯片吞吐率均大大低于专用芯片,因此,如何提高处理速度是可重构密码芯片设计的关键问题.本文分析了常用对称密码算法DES、3DES和AES的可重构性,利用流水线、并行处理和可重构技术,提出了一种可重构体系结构.基于该体系结构实现的DES、3DES和AES吞吐率在110MHz工作频率下分别可达到7Gbps、2.3Gbps和1.4Gbps.与其他同类设计相比,本文设计在处理速度上有较大优势,可以很好地应用到可重构密码芯片设计中.

A Reconfigurable Architecture for High-Speed Implementations of DES ,3DES and AES

A reconfigurable cipher chip, which can improve the security and flexibility,has good potential to become a vital component in the future security system. However, the throughput of most reconfigurable cipher chips is pretty lower than that of specific purpose chips. How to improve the throughput becomes more and more important. In this paper,based on the analysis about the reconfiguration of the DES ,3DES and AES ,we propose a reconfigurable architecture, which combines reconfiguration technology with pipeline, parallel structure. We also implement DES,3DES, AES algorithms based on the reconfiguration architecture. The simulations show that the throughput is 7Gbps for DES, 2.3Gbps for 3DES and 1.4Gbps for AES under a 110MHz clock. Moreover,the comparison with other current designs shows that the solution proposed in this paper achieves better performance than other solutions, and thus is suitable to the design of reconfigurable cipher chips.