10.4~28 GHz的超宽带6位数字衰减器设计

基于中芯国际40 nm CMOS工艺设计并实现了一种超宽带6位数字衰减器,其工作频率为10.4～28 GHz。该衰减器采用内嵌式开关型结构,6位衰减单元的设计采用T型、桥T型和π型三种拓扑结构。该6位衰减器可以实现0.5 dB的衰减步进,31.5 dB的动态衰减范围。采用大衰减量幅度补偿电路和高匹配特性的衰减位级联结构,衰减器在10.4～28 GHz的频段范围内具有平坦的64态衰减量,衰减器的整体前仿真插入损耗为1.73～2.08 dB,后仿真插入损耗为4.32～6.31 dB,64态的输入输出回波损耗均小于-10 dB。

Design of a 10.4-28 GHz Ultra-Wideband Six-bit Digital Attenuator

An ultra-wideband six-bit digital attenuator operating at frequencies ranging from 10.4 GHz to 28 GHz was designed and implemented in SMIC 40 nm CMOS process. The attenuator utilized an embedded switching-type structure, with the six-bit attenuation unit designed in three different topologies, T-type, bridge-T-type, and π-type. This six-bit attenuator achieves a step attenuation of 0.5 dB and a dynamic attenuation range of 31.5 dB. By incorporating a large attenuation amplitude compensation circuit and a cascaded structure of attenuation bits with excellent matching characteristics, the attenuator achieves a flat 64-state attenuation across the frequency range of 10.4 GHz to 28 GHz. The pre-simulation insertion loss of the attenuator ranges from 1.73 dB to 2.08 dB, while the post-simulation insertion loss ranges from 4.32 dB to 6.31 dB. Furthermore, the input and output return losses of all 64-states are less than -10 dB.